1. Field of the Invention
The present invention relates to a bit error rate tester and a pseudo random bit sequences generator thereof, and more particularly, to a parallel bit error rate tester and a parallel pseudo random bit sequences generator thereof.
2. Description of the Related Art
A pseudo random bit sequences (PRBS) generator is commonly used in a data transceiver as a source for testing input signals. FIG. 1 schematically shows a conventional data transmitting and receiving system having a serial bit error rate tester. When a transmitter 110 intends to transmit data to a receiver 120 via a transmission media 130 (e.g. a cable), a master system 111 in the transmitter 110 provides a parallel data to a serializer 112. The serializer 112 converts the parallel data to a serial data, then a driver 115 transmits the serial data to an input-buffer 125 in the receiver 120 via the transmission media 130. A deserializer 122 converts the serial data, which is output from the transmitter 110 and has passed through the transmission media 130 and the input-buffer 125, to a parallel data, such that the serial data is further transmitted to a master system 121 in the receiver 120.
Conventionally, when measuring the bit error rate between the transmitter 110 and the receiver 120, a bit error rate tester 113 in the transmitter 110 generates a serial pseudo random bit sequences Dout, then a multiplexer 114 selectively transmits the pseudo random bit sequences Dout to the driver 115, and the driver 115 transmits the serial pseudo random bit sequences to the input-buffer 125 in the receiver 120 via the transmission media 130. Meanwhile, a demultiplexer 124 selectively transmits the received pseudo random bit sequences to a bit error rate tester 123. The bit error rate tester 123 counts the number of error bits on the received pseudo random bit sequences, such that the bit error rate is obtained.
In general, each of the bit error rate testers 113 and 123 comprises a serial pseudo random bit sequences generator for generating same pseudo random bit sequences. FIG. 2 schematically shows a conventional serial pseudo random bit sequences generator. The serial pseudo random bit sequences generator comprises a plurality of registers 210-1˜210-15 and an XOR gate 220. When a clock starts, each output of the registers 210-1˜210-15 is transmitted to the next register, the XOR gate 220 performs an operation on an output of the register 210-14 and an output of the register 210-15, and the operation result is fed back to the input of the first register 210-1. If not all initial values of the registers are 0, by repeatedly performing such operation, all combination signals except the one equals to all 0 should be generated, and the output data Dout is commonly used as the generated pseudo random bit sequences.
In order to improve the applications of the pseudo random bit sequences generator and to increase its testability, a programmable pseudo random bit sequences generator is necessary. FIG. 3 schematically shows a conventional programmable pseudo random bit sequences generator configuration. As shown in the diagram, a plurality of serial registers 310-1˜310-31 sequentially transmits the pseudo random bit sequences Dout stage by stage based on the clock signal, and the XOR gate performs a different algorithm operation on the outputs of part of the registers 310-1˜310-31, and the operation result is fed back to a multiplexer 330, such that a plurality of feedback paths is formed. The multiplexer 330 selects the feedback path representing different algorithm as the active feedback path based on a selection signal SEL, so as to modify the pattern length of the output pseudo random bit sequences.
However, under extremely high speed application conditions, the bit rate of the conventional serial pseudo random bit sequences generator is restrained by the speed of the digital circuits and the registers. Besides, due to the registers are operated in an utmost speed, a great amount of power consumption is inevitable. In addition, a conventional data transmission system is typically configured as multi-bit parallel input, serial transmission, and multi-bit serial output, the conventional serial bit error rate tester is not able to fully test each component in the entire transmission testing system (for example, the serializer 112 and the deserializer 122 of FIG. 1 are not testable).